| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 107 === Multi-phase buck converter configuration with constant on-time (COT) control scheme has been widely used in many high-efficiency, low-voltage high-current computer power applications. To avoid thermal issue and increase efficiency, a current balance control scheme is required to balance per-phase inductor currents. However, it lacks comprehensive analysis and design of current balance loop in literature.
In this thesis, analyses are performed for several aspects of the above-mentioned converter-controller configuration. First, per-phase D.C. current equations are derived for COT control scheme with current balance loop. From the equations, the relation between component parameters and current distribution can be obtained. Second, Monte Carlo results give a reference to choose mismatch range of component and design current balance loop parameter to meet the current balance specification. Third, small-signal models are developed which can be used to predict stability and transient response performance. Besides, the relation between the current balance loop and the voltage regulation loop is discussed. The analytical results provide a design guideline of the current balance loop. Finally, the proposed model was verified with experimental results.
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