Nanometer-scale transistor with high driving capability

• Main Authors: Yi-Wei Chao, 趙奕惟
• Other Authors: Miin-Horng Juang
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/kt3843

碩士 === 國立臺灣科技大學 === 光電工程研究所 === 107 === As described by Moore's Law, proposed by Intel co-founder Gordon Moore, the number of transistors that can be accommodated on an integrated circuit is doubled every two years, and the behind-the-scenes push for such growth is wafer miniaturization. What is created, but the conventional metal oxide semiconductor device will have some reliability problems after miniaturization, such as the hot carrier effect in the short channel effect, the gate leakage current (GIDL), punch through, etc. These have a very large impact on the electrical properties of the components themselves, so it is necessary to try to solve these problems. Since the junctionless transistor does not have p-type doping to block the punch through, the leakage current has a poor suppression performance compared with the general transistor. The purpose of this paper is to simulate the change of the device structure and its related parameters. This thesis proposes a trench-gate junctionless transistor to trigger the p-n junction diode. The trench-gate is employed to improve poor leakage characteristics, and the embedded p+ region in the n+ drain region can also form an energy barrier to suppress leakage current. In addition, due to the embedded p-n junction diode, the output current is significantly increased. As a result, as compared to the conventional metal oxide field effect transistor with miniaturization, the device structure can effectively improve the leakage characteristics and enhance the output current.