Synchronization and System Integration for Low-Data-Rate Wireless Network

• Main Authors: Yu-Jyue Lin, 林鈺玨
• Other Authors: Huan-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/ne4788

碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === Many industries are using new model to develop business due to the Internet of Things (IoT) is expanding at a rapid rate. The feature of IoT is small, light, low power consumption and low cost, so we use WARP V3 Reference Design which based on the Standard of IEEE 802.11a/g and OFDM PHY’s transceiver to achieve narrow bandwidth and low carrier frequency. In order to implement the transceiver for IoT, predecessor integrated the RF AD9361 into the system, but AD9361 has larger frequency offset which cause higher packet error rate (PER); and further, WARP V3 Reference Design cannot demodulation successfully at frequency offset up to 40 ppm. The purpose of this thesis is to design synchronization algorithm which based on WARP V3 reference design, and implement the low-data-rate WLAN. To meet this goal, subcarrier spacing should be reduced, also the time to transmit and receive packet should be increased, which makes OFDM modulation more sensitive to carrier frequency offset and sample frequency offset. Therefore, the main goal of this thesis is to propose a new algorithm for frequency offset estimation. Finally, we use the FPGA board to verify our algorithm.