Design and Implementation of an IP Compatible with the ARM Cortex-M3 ISA

• Main Authors: Zi-Chang Su, 蘇子暢
• Other Authors: Ming-Bo Lin
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/buz8zv

碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === With the prosperity of embedded system applications such as information appliances and internet of things, the needs of microprocessors for embedded system grow rapidly. The largest supplier of microprocessors for embedded system in the world is ARM. The ARM microprocessors, compare with other microprocessors, have the advantages of high efficiency and low power consumption. The ARM Cortex-M3 microprocessor which is designed for embedded system especially, has a 3-stage pipeline with the Harvard architecture. The Cortex-M3 microprocessor supports only thumb and thumb-2 instruction sets instead of the ARM instruction set, and hence increases the instruction density as well as reduces the requirement of instruction memory. In this thesis, we implement an IP compatible with the ARM Cortex-M3 ISA with the Xilinx Virtex-5 XC5VLX110T FPGA. Our design consumes 4917 LUTs and 698 registers, and operates at the maximum frequency of 30.5MHz.