| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === In the RF integrated circuits (IC) , PLL are very important block of the transceiver circuit, PLL characteristics include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider, this thesis presents the design of Injection-locked frequency dividers (ILFDs).
First, a Wide-Locking Range Divide-by-6 Injection-Locked Frequency Divider Using Linear Mixer Approach (ILFD) using a standard 0.18 μm BiCMOS process is presented. The die area is 855.42×954.492 μm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses extra capacitive cross-coupled to enhance the locking range , therefore we found maximum locking range at 13.2 GHz ~ 16 GHz (19.86%). But the best performance of the chip is at supply voltage 0.95 V, the power consumption of the ILFD core is 5.6 mW and the locking range is from 14.5 GHz ~ 16.3 GHz (11.69%) at injection power Pinj = 0 dBm.
Secondly, a 5:1 LC-resonator Injection-Locked Frequency Dividers (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-5 ILFD uses double capacitive cross-coupled oscillator. At the power supply of 0.95 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-5 ILFD is 3.8 GHz (27.34%) from 12 to 15.8 GHz, the ILFD has overlapped locking ranges. The core power consumption is 5.11 mW. The die area is 855.42×954.492 μm2.
Third, a Wide-Band Harmonic Mixer Divide-by-4 Injection-Locked Frequency Divider (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-4 ILFD uses double capacitive cross-coupled oscillator and mutual inductors combine with a pair of varactors. At the power supply of 0.95 V, and at the incident power of 0 dBm, the locking range of the divide-by-4 ILFD is 3.9 GHz, from the incident frequency 10.1 to 14 GHz and the locking range percentage is 32.37%. The die area is 1006.28 × 925.377 μm2. The power consumption of ILFD core is 2.61 mW.
Finally, a Double Capacitive Cross-Coupled Divide-by-3 Injection-Locked Frequency Divider (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-3 ILFD uses double capacitive cross-coupled oscillators. At the power supply of 0.9 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-3 ILFD is 4.7 GHz (54.33%) from 12 to 15.8 GHz, the ILFD has overlapped locking ranges. The core power consumption is 4.45 mW. The die area is 855.42×954.492 μm2.
|
|---|
