| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 107 === Due to rapid advance of the IC technology, design complexity is dramatically increasing in printed circuit boards (PCBs). Nowadays, a dense PCB contains
thousands of pins and signal nets, such huge net counts make manual design of
PCBs an extremely time-consuming task especially in the routing phase. Bus routing, which consists of assigning all the buses to the routing layers and topologically routing them on each layer while satisfying some constraints, is one of the most difficult steps in PCB routing. Besides, timing constraints are commonly concerned on PCB bus structure, where all bits of buses are highly preferred to have approximately same length, so that length-matching issue is often requested. In advanced technology nodes, moreover, routing tracks are provided to help router adhere to design rules and help mask coloring. In this thesis, we develop a sophisticated bus router which optimizes routability, wirelength, as well as length-matching while simultaneously considering track resources, obstacles, and other design constraints. Experimental results show that the proposed algorithm flow can outperform the state-of-the-art bus routers [18] [19] in terms of the total routing cost and the min-max length difference for the benchmarks provided by 2018 CAD contest at ICCAD[17].
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