| Summary: | 碩士 === 國立高雄大學 === 電機工程學系碩博士班 === 107 === To meet the demand for small devices required for future high-stack density circuits, three-dimensional devices with good short-channel control behavior and high stacking density, such as Triple-Gate MOSFETs, Quadruple-gate MOSFETs and Omega-Gate MOSFETs replace traditional planar transistors that scarce short-channel control characteristics. In recent years, in order to solve many devices and process problems, a Tunnel Field-Effect transistor has been proposed, which has a Subthreshold Slope (SS) that can exceed the limit of 60mV / dec and the small off-state current; therefore, it's suitable for applications in low power circuits. In the past few decades, although there have been studies on the subthreshold behavior of Multiple-Gate MOSFETs and Double-gate TFET, it is still quite lacking the research on the influence of devices with the variety of electrical parameters for Multiple-Gate MOSFETs and the analysis of 3-D device of Multiple-Gate tunnel field-effect transistors (TFETs). In this thesis, we will focus on changing the device parameters to analysis the behavior that from device to its application in the logic circuit.
Based on the quasi-2-D/3-D solution of the Poisson’s equation, scaling theory and perimeter-weighted-ratio, this thesis successfully propose the behavior model for Multiple-Gate FETs. This model not only shows the potential distribution, the subthreshold slope, drain-induced barrier lowering (DIBL), drain-induced barrier thinning (DIBT), threshold voltage roll-off and the drain current but also can be used to analyze the DC behavior of the logic circuit, such as noise margin, logic swing and average DC power consumption. All of the models provide a basic guidance to design the MG devices and the logic circuits.
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