A 12bit Successive Approximation Analog-to-Digital Converter for Electrochemical Analysis

• Main Authors: LIN, YOU-REN, 林祐任
• Other Authors: Lee, Da-Huei
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/p8x27j

碩士 === 南臺科技大學 === 電子工程系 === 107 === As the era progresses towards a smart life, many products are also advancing to include more science and technology, such as in daily necessities, wearable devices, medical supplies and others. However, most of these products require an analog-to-digital converter to change discrete signals into digital forms for analysis. An electrochemical measuring device is an important bridge of data transmission; thus, it is possible to reduce the device into smaller and portable form, while the medium used in contact should be more affordable, as well as disposable. Cyclic voltammetry of electrochemistry in this study was one of the most commonly used methods. Primarily, a potential function was first applied to generate a current for analysis. The potential scan would start with a positive potential or potential and returned in a cycle after reaching the terminal potential, in which such cycle could allow the plotting of CV for the oxidation reaction. A tri-electrode system was used, where screen printing used three electrodes, which were respectively the working electrode, the reference electrode and the auxiliary electrode. The 12-bit successive-approximation analog-to-digital converter was used in this study, with the algorithm based on binary search, where the intermediate value was used for comparison and the comparative result was temporarily registered each time, until successively approximated to the exact value of the input voltage drop. The architecture of the analog-to-digital converter included a sample-and-hold circuit, a comparator circuit and a successive-approximation logic control circuit, a control switch circuit and a capacitor array circuit. By double-ended differential input, the system could be effectively shielded from noises and it would be quite helpful for signal accuracy. The capacitor array was consisted of MOM capacitors (Metal-oxide-metal) and used five layers of metal in form of Pillar structure, in order to constitute a small unit capacitance value. When the sampling frequency is 8.928571429 MHz and clock of 125MHz. The signal-to-noise ratio during pre-simulation was 72.704 dB and the effective bit was 12.3694 bits. SNDR of post-simulation was 47.2578 dB and the effective bit was 8.1425 bits. The circuit layout used a TSMC 0.18μm CMOS process, with a size of 1.2mm x 1.2mm.