Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars

• Main Authors: LI, CHI-HSUAN, 李奇軒
• Other Authors: WANG, SEN
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/4q32b5

碩士 === 國立臺北科技大學 === 電子工程系 === 107 === In this thesis, there are two keys block diagram for X-band FMCW radars. One is the PA, the other is receiver. These are fabricated by standard 0.18-m 1P6M CMOS. Above all, the design of PA in chapter 3. This design consists of a two-stage common-source (CS) PA and cold-FET pre-distortion (PD). The chip size is 1.175 x 1.0 mm2 and consumed dc power of 93mW when input power was 0 dBm at 12 GHz. Meanwhile, the PA achieved output 1-dB gain compression point (OP¬1dB) 15.5 dBm with 5 dB improvement by PD and the saturation output power (Psat) 17.4 dBm with 22% of peak power-added efficiency (PAE) at 8.9 dBm from 1.8-V voltage supply. In the chapter 4, the proposed of receiver using active balun. The design consists of active balun, low noise amplifier (LNA), and Gilbert-celled double-balanced mixer. The chip size is 1.2 x 1.2 mm2 and consumed a dc power of 35mW when LO input power was 0 dBm at 12 GHz. The proposed receiver has the conversion gain (CG) of 17 dB, double-sideband noise figure (NF) of 11 dB. Finally, review and conclusion in chapter 5.