Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars
碩士 === 國立臺北科技大學 === 電子工程系 === 107 === In this thesis, there are two keys block diagram for X-band FMCW radars. One is the PA, the other is receiver. These are fabricated by standard 0.18-m 1P6M CMOS. Above all, the design of PA in chapter 3. This design consists of a two-stage common-source (CS) PA...
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ndltd-TW-107TIT004270192019-11-09T05:23:21Z http://ndltd.ncl.edu.tw/handle/4q32b5 Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars X頻段CMOS雷達之功率放大器與接收機研製 LI, CHI-HSUAN 李奇軒 碩士 國立臺北科技大學 電子工程系 107 In this thesis, there are two keys block diagram for X-band FMCW radars. One is the PA, the other is receiver. These are fabricated by standard 0.18-m 1P6M CMOS. Above all, the design of PA in chapter 3. This design consists of a two-stage common-source (CS) PA and cold-FET pre-distortion (PD). The chip size is 1.175 x 1.0 mm2 and consumed dc power of 93mW when input power was 0 dBm at 12 GHz. Meanwhile, the PA achieved output 1-dB gain compression point (OP¬1dB) 15.5 dBm with 5 dB improvement by PD and the saturation output power (Psat) 17.4 dBm with 22% of peak power-added efficiency (PAE) at 8.9 dBm from 1.8-V voltage supply. In the chapter 4, the proposed of receiver using active balun. The design consists of active balun, low noise amplifier (LNA), and Gilbert-celled double-balanced mixer. The chip size is 1.2 x 1.2 mm2 and consumed a dc power of 35mW when LO input power was 0 dBm at 12 GHz. The proposed receiver has the conversion gain (CG) of 17 dB, double-sideband noise figure (NF) of 11 dB. Finally, review and conclusion in chapter 5. WANG, SEN 王紳 2019 學位論文 ; thesis 61 en_US |
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碩士 === 國立臺北科技大學 === 電子工程系 === 107 === In this thesis, there are two keys block diagram for X-band FMCW radars. One is the PA, the other is receiver. These are fabricated by standard 0.18-m 1P6M CMOS.
Above all, the design of PA in chapter 3. This design consists of a two-stage common-source (CS) PA and cold-FET pre-distortion (PD). The chip size is 1.175 x 1.0 mm2 and consumed dc power of 93mW when input power was 0 dBm at 12 GHz. Meanwhile, the PA achieved output 1-dB gain compression point (OP¬1dB) 15.5 dBm with 5 dB improvement by PD and the saturation output power (Psat) 17.4 dBm with 22% of peak power-added efficiency (PAE) at 8.9 dBm from 1.8-V voltage supply.
In the chapter 4, the proposed of receiver using active balun. The design consists of active balun, low noise amplifier (LNA), and Gilbert-celled double-balanced mixer. The chip size is 1.2 x 1.2 mm2 and consumed a dc power of 35mW when LO input power was 0 dBm at 12 GHz. The proposed receiver has the conversion gain (CG) of 17 dB, double-sideband noise figure (NF) of 11 dB. Finally, review and conclusion in chapter 5.
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author2 |
WANG, SEN |
author_facet |
WANG, SEN LI, CHI-HSUAN 李奇軒 |
author |
LI, CHI-HSUAN 李奇軒 |
spellingShingle |
LI, CHI-HSUAN 李奇軒 Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
author_sort |
LI, CHI-HSUAN |
title |
Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
title_short |
Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
title_full |
Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
title_fullStr |
Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
title_full_unstemmed |
Design and Implementation of Receiver and Power Amplifier for X-band CMOS Radars |
title_sort |
design and implementation of receiver and power amplifier for x-band cmos radars |
publishDate |
2019 |
url |
http://ndltd.ncl.edu.tw/handle/4q32b5 |
work_keys_str_mv |
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