Chip Design and Implementation of Current Mode DC-DC Buck Converter with Pulse Width Modulation and Pulse Frequency Modulation

• Main Authors: HSIEH, SHIH-YU, 謝適宇
• Other Authors: SUNG,GUO-MING
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/9y6zah

碩士 === 國立臺北科技大學 === 電機工程系 === 107 === Display technology plays an essential role in variety of electronic products. The techical trend indicates that the small display performs with small chip size and low power consumption, such as mobile devices, wearable devices, automotive devices, laptops and so on. These devices make a wonderful life with power management IC, which provides stable voltage with small voltage ripple. The smaller the voltage ripple is, the better the performance of display is. This thesis presents the chip design and implemention of current DC-DC buck converter with pulse width modulation and frequency pulse modulation. The proposed chip in composed of the error amplifier、hystersis compator、ramp generator、non-overlaping circuit and soft-start circuit. Note that the current feedback performs with faster response to provide a stable output voltage. Besides, the converter is operating in frequency pulse modulation (PFM) mode with the light current loading. when it switches to pulse width modulation (PWM) mode when the converter operates with medium or heavy current loading. By integrating the PFM mode with PWM mode, the converter can achieve a high power efficiency at all current loading. The proposed chip is implemention in 0.18 μm 1P3M process. The output voltage ranges from 0.9V~2.1V at the input voltage ranging from 2.5V to 5.0V, The mesument shows that the output voltage is 3.3V and maximum power efficiency is 92.32% at the input voltage of 1.8V and the current loading of 400mA.