Iris : an integrated circuit layout automatic generator
In integrated circuit design, layout generation is tedious, time-consuming and error-prone. Motivated by seeking an alternative to manual layout design, I implmented a CAD tool, Iris, dedicating to layout generation automation. By using Iris, the designer describes the circuit netlist and relative p...
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| Format: | Others |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/2429/14573 |
| Summary: | In integrated circuit design, layout generation is tedious, time-consuming and error-prone. Motivated by seeking an alternative to manual layout design, I implmented a CAD tool, Iris, dedicating to layout generation automation. By using Iris, the designer describes the circuit netlist and relative placement of each transistor and signal in the high level language Java. Iris works out the details of every design stage and produces the final layout. Experimental results show that Iris generates layouts which are comparable to manual layouts with much less effort by the designer. === Science, Faculty of === Computer Science, Department of === Graduate |
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