Characterization and modeling of crosstalk bounded uncorrelated jitter (Buj) for high-speed interconnects

As data rates move towards the Gbps regime, effects that may have been ignored at lower data rates are becoming significant. Such signal integrity issues decrease the timing budget of I/O interconnects exponentially and hence, place a stringent requirement on the total jitter budget. The issues that...

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Bibliographic Details
Main Author: Kuo, Andy
Format: Others
Language:English
Published: 2009
Online Access:http://hdl.handle.net/2429/15577
Description
Summary:As data rates move towards the Gbps regime, effects that may have been ignored at lower data rates are becoming significant. Such signal integrity issues decrease the timing budget of I/O interconnects exponentially and hence, place a stringent requirement on the total jitter budget. The issues that affect signal integrity also affect jitter as both share many common root causes. Jitter can be divided into different subcomponents each with different root causes and properties. Crosstalk Jitter, or commonly referred in the industry as Bounded Uncorrelated Jitter (BUJ), is a jitter subcomponent that is mostly caused by crosstalk coupling from the adjacent interconnects on printed-circuit boards (PCB). However, the characteristics of BUJ are still ill understood. In addition, a mathematical model of jitter and an algorithm to generate a histogram for BUJ have not been developed to this date. The crosstalk-induced pulse characteristic from an aggressor signal is studied here. Based on the superposition principle, a jitter model to calculate the time difference between the distortion-free and the distorted edge crossings was developed. This model is also extended to calculate the worst-case timing difference. In addition, algorithms to generate the histogram distributions of BUJ are also developed. Simulation and measurement results validate the BUJ model. Algorithms developed to generate the histogram for BUJ show reasonable accuracy with four aggressor traces or less. These algorithms have fast execution times of 5~20 seconds, compared to simulation and measurement times in the range of 10~30 minutes, which require data post-processing. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate