Implementation of standard cell library with low power consumption.

• Main Author: Rasmusson, Oscar
• Format: Others
• Language: English
• Published: Linköpings universitet, Institutionen för systemteknik 2003
• Subjects: Electronics; Cellbibliotek; Standardcell; 0.18; CMOS; låg effektförbrukning.; Elektronik
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1917

I 0.18 µm CMOS process har ett standardcells bibliotek med låg effektförbrukning implementerats. Cellerna har konstruerats och simulerats i Cadence och ett layoutprogram. Vid simulering av heladderare och D-vippor har effektförbrukningen och tider mätts upp och jämförts med varandra. Matningsspänningen varierade mellan 1 V och 1.8 V. In 0.18 µm CMOS process has a standard cell library with low power consumption been implemented. The cells have been made and simulated in Cadence and a layout program. At the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V. === A standard cell library with low power consumption has been implemented in a 0.18 mm CMOS process. The cells have been designed and simulated in Cadence and a layout program. During the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.