Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35um Process

• Main Author: Johansson, Robert
• Format: Others
• Language: English
• Published: Linköpings universitet, Institutionen för systemteknik 2003
• Subjects: Electronics; APS; ASIC; CDS; CMOS; Image; Pixel; Sensor; Shutter; Vision; VLSI; Elektronik
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1927

An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design. Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippetsinto actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated. Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible. The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.