Temperature Aware and Defect-Probability Driven Test Scheduling for System-on-Chip
The high complexity of modern electronic systems has resulted in a substantial increase in the time-to-market as well as in the cost of design, production, and testing. Recently, in order to reduce the design cost, many electronic systems have employed a core-based system-on-chip (SoC) implementatio...
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| Format: | Doctoral Thesis |
| Language: | English |
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Linköpings universitet, ESLAB - Laboratoriet för inbyggda system
2010
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56514 http://nbn-resolving.de/urn:isbn:978-91-7393-378-0 |