Design of a Voltage Controlled Oscillator for Galileo/GPS Receiver
The main aim of this thesis is to implement a voltage-controlled oscillator for a Galileo/GPS receiver with a center frequency of 1.5 GHz in 150 nm CMOS process. As the designed VCO has to be integrated in a phase locked loop, VCO gain is selected high enough for the PLL to lock even with process va...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2012
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76279 |
| Summary: | The main aim of this thesis is to implement a voltage-controlled oscillator for a Galileo/GPS receiver with a center frequency of 1.5 GHz in 150 nm CMOS process. As the designed VCO has to be integrated in a phase locked loop, VCO gain is selected high enough for the PLL to lock even with process variations. A new state of art architecture called double harmonic tuned VCO is selected and designed for this GPS application. It uses a complex combination of inductors and capacitors to reduce phase-noise of the VCO by suppressing second harmonic oscillations in the tail node of VCO. The designed VCO shows significant improvement in phase-noise performance compared to a normal LC tank VCO by reducing phase-noise around 4 dBc/Hz. The VCO has a phase-noise of -128 dBc/Hz at 1 MHz offset from center frequency with a power consumption of 5 mW and a tuning range of about 257 MHz for a 1 V tuning voltage range. |
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