Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology

Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso de...

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Bibliographic Details
Main Author: Ebrahimi Mehr, Golnaz
Format: Others
Language:English
Published: Linköpings universitet, Elektroniska komponenter 2013
Subjects:
Rom-Less DDFS
Current Steering Digital-to-Analog Converter
Interleaved DACs
Return-to-Zero
Sine weighted DAC
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680
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spelling ndltd-UPSALLA1-oai-DiVA.org-liu-916802013-04-30T04:16:50ZDesign of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS TechnologyengEbrahimi Mehr, GolnazLinköpings universitet, Elektroniska komponenterLinköpings universitet, Tekniska högskolan2013Rom-Less DDFSCurrent Steering Digital-to-Analog ConverterInterleaved DACsReturn-to-ZeroSine weighted DACA 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks. Student thesisinfo:eu-repo/semantics/bachelorThesistexthttp://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680application/pdfinfo:eu-repo/semantics/openAccess
collection NDLTD
language English
format Others
sources NDLTD
topic Rom-Less DDFS
Current Steering Digital-to-Analog Converter
Interleaved DACs
Return-to-Zero
Sine weighted DAC
spellingShingle Rom-Less DDFS
Current Steering Digital-to-Analog Converter
Interleaved DACs
Return-to-Zero
Sine weighted DAC
Ebrahimi Mehr, Golnaz
Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
description A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.
author Ebrahimi Mehr, Golnaz
author_facet Ebrahimi Mehr, Golnaz
author_sort Ebrahimi Mehr, Golnaz
title Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
title_short Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
title_full Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
title_fullStr Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
title_full_unstemmed Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
title_sort design of a rom-less direct digital frequency synthesizer in 65nm cmos technology
publisher Linköpings universitet, Elektroniska komponenter
publishDate 2013
url http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680
work_keys_str_mv AT ebrahimimehrgolnaz designofaromlessdirectdigitalfrequencysynthesizerin65nmcmostechnology
_version_ 1716584983252959232

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