Self Reconfiguration of Clock Networks on FPGA : Methodology for partial reconfiguration of synchronous modules at run-time
In this thesis, methodology for partial self-reconfiguration of synchronous modules has been developed. A simple software-based scheduler has been built for scheduling synchronous modules on the FPGA. The motivation behind this was that partial reconfiguration of synchronous modules at run-time had...
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| Format: | Others |
| Language: | English |
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Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon
2011
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13641 |