A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage
The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash or successive approximation ADC techniques. The high-resolution, high-speed requirements can relatively easier be achieved usi...
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ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-240102015-09-20T17:22:35ZA study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stageBayoumy, Mostafa ElsayedPipeline ADC1.5-bit stageThe demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash or successive approximation ADC techniques. The high-resolution, high-speed requirements can relatively easier be achieved using pipelined architecture ADC’s than other implementations of ADC’s of the same requirements. Because the stages work simultaneously, the number of stages needed to obtain a certain resolution is not constrained by the required throughput rate. Latency is a result of a multistage concurrent operation of any pipelined system. But luckily enough, latency isn’t considered to be a problem in many ADC applications. In this work, a 1.5-bit stage in the pipeline ADC is completely implemented including its two voltage comparators, a DAC with three possible output voltages, and a multiplying digital to analog (MDAC) blocks. Only ideal components were used for clocking operation. At the end of design, a total harmonic distortion (THD) of less than -70 dB was achieved.text2014-04-15T19:54:24Z2013-122014-01-23December 20132014-04-15T19:54:25ZThesisapplication/pdfhttp://hdl.handle.net/2152/24010 |
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Pipeline ADC 1.5-bit stage |
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Pipeline ADC 1.5-bit stage Bayoumy, Mostafa Elsayed A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
description |
The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash or successive approximation ADC techniques. The high-resolution, high-speed requirements can relatively easier be achieved using pipelined architecture ADC’s than other implementations of ADC’s of the same requirements. Because the stages work simultaneously, the number of stages needed to obtain a certain resolution is not constrained by the required throughput rate. Latency is a result of a multistage concurrent operation of any pipelined system. But luckily enough, latency isn’t considered to be a problem in many ADC applications. In this work, a 1.5-bit stage in the pipeline ADC is completely implemented including its two voltage comparators, a DAC with three possible output voltages, and a multiplying digital to analog (MDAC) blocks. Only ideal components were used for clocking operation. At the end of design, a total harmonic distortion (THD) of less than -70 dB was achieved. === text |
author |
Bayoumy, Mostafa Elsayed |
author_facet |
Bayoumy, Mostafa Elsayed |
author_sort |
Bayoumy, Mostafa Elsayed |
title |
A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
title_short |
A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
title_full |
A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
title_fullStr |
A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
title_full_unstemmed |
A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage |
title_sort |
study of 10-bit, 100msps pipeline adc and the implementation of 1.5-bit stage |
publishDate |
2014 |
url |
http://hdl.handle.net/2152/24010 |
work_keys_str_mv |
AT bayoumymostafaelsayed astudyof10bit100mspspipelineadcandtheimplementationof15bitstage AT bayoumymostafaelsayed studyof10bit100mspspipelineadcandtheimplementationof15bitstage |
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1716823716920295424 |