Sequential redundancy identification using transformation-based verification
The design of complex digital hardware is challenging and error-prone. With short design cycles and increasing complexity of designs, functional verification has become the most expensive and time-consuming aspect of the digital design process. Sequential equivalence checking (SEC) has been proposed...
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| Format: | Others |
| Language: | English |
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2008
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| Online Access: | http://hdl.handle.net/2152/3890 |