Multimodule simulation techniques for chip level modeling

Multimodule simulation techniques for chip level modeling

M.S.

Bibliographic Details
Main Author: Cho, Chang H.
Other Authors: Electrical Engineering
Format: Others
Language:en
Published: Virginia Polytechnic Institute and State University 2021
Subjects:
LD5655.V855 1986.C562
Digital computer simulation
Electronic digital computers > Design > Data processing
Logic design > Data processing
Online Access:http://hdl.handle.net/10919/106085
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spelling ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-1060852021-10-28T05:34:43Z Multimodule simulation techniques for chip level modeling Cho, Chang H. Electrical Engineering LD5655.V855 1986.C562 Digital computer simulation Electronic digital computers -- Design -- Data processing Logic design -- Data processing M.S. 2021-10-26T20:10:04Z 2021-10-26T20:10:04Z 1986 Thesis Text http://hdl.handle.net/10919/106085 en OCLC# 13958044 In Copyright http://rightsstatements.org/vocab/InC/1.0/ viii, 114 leaves application/pdf application/pdf Virginia Polytechnic Institute and State University
collection NDLTD
language en
format Others
sources NDLTD
topic LD5655.V855 1986.C562
Digital computer simulation
Electronic digital computers -- Design -- Data processing
Logic design -- Data processing
spellingShingle LD5655.V855 1986.C562
Digital computer simulation
Electronic digital computers -- Design -- Data processing
Logic design -- Data processing
Cho, Chang H.
Multimodule simulation techniques for chip level modeling
description M.S.
author2 Electrical Engineering
author_facet Electrical Engineering
Cho, Chang H.
author Cho, Chang H.
author_sort Cho, Chang H.
title Multimodule simulation techniques for chip level modeling
title_short Multimodule simulation techniques for chip level modeling
title_full Multimodule simulation techniques for chip level modeling
title_fullStr Multimodule simulation techniques for chip level modeling
title_full_unstemmed Multimodule simulation techniques for chip level modeling
title_sort multimodule simulation techniques for chip level modeling
publisher Virginia Polytechnic Institute and State University
publishDate 2021
url http://hdl.handle.net/10919/106085
work_keys_str_mv AT chochangh multimodulesimulationtechniquesforchiplevelmodeling
_version_ 1719491603839582208

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