Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development

• Main Author: Djigbenou, Jeannette Donan
• Other Authors: Electrical and Computer Engineering
• Format: Others
• Published: Virginia Tech 2014
• Subjects: VLSI design; CAD Tools; Standard cell library; Automation; ASIC design; Quality Assurance; CMOS technologies
• Online Access: http://hdl.handle.net/10919/32269; http://scholar.lib.vt.edu/theses/available/etd-05062008-204445/

Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us. === Master of Science