Development of a Low-Power SRAM Compiler
Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In...
Main Author: | Jagasivamani, Meenatchi |
---|---|
Other Authors: | Electrical and Computer Engineering |
Format: | Others |
Published: |
Virginia Tech
2014
|
Subjects: | |
Online Access: | http://hdl.handle.net/10919/34963 http://scholar.lib.vt.edu/theses/available/etd-09082000-03290016/ |
Similar Items
-
DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC
by: A. KISHORE KUMAR, et al.
Published: (2014-12-01) -
Design and Analysis of Low-power SRAMs
by: Sharifkhani, Mohammad
Published: (2007) -
Design and Analysis of Low-power SRAMs
by: Sharifkhani, Mohammad
Published: (2007) -
A Robust Low Power Static Random Access Memory Cell Design
by: Pusapati, A. V. Rama Raju
Published: (2018) -
Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator
by: Åkerman, Markus
Published: (2005)