An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms
Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS, which reduces CPU energy consumption throug...
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ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-350352020-09-26T05:37:31Z An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms Saha, Sonal Electrical and Computer Engineering Ravindran, Binoy Plassmann, Paul E. Broadwater, Robert P. Dynamic Voltage and Frequency Scaling Real-Time Linux Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS, which reduces CPU energy consumption through DVFS, while at the same time ensures that task time constraints are satisfied by constructing appropriate real-time task schedules. The literature presents numerous RT-DVFS scheduling algorithms, which employ different tech- niques to utilize the CPU idle time to scale the frequency. Many of these algorithms have been experimentally studied through simulations, but have not been implemented on real hardware platforms. Though simulation-based experimental studies can provide a first-order understanding, implementation-based studies can reveal actual timeliness and energy con- sumption behaviours. This is particularly important, when it is difficult to devise accurate simulation models of hardware, which is increasingly the case with modern systems. In this thesis, we study the timeliness and energy consumption behaviours of fourteen state- of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware plat- forms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others, and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother- board with the AMD Zacate processor. We implemented these schedulers in the ChronOS real-time Linux kernel and measured their actual timeliness and energy behaviours under a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock- intensive, and processor-underloaded and overloaded workloads. Our studies reveal that measuring the CPU power consumption as the cube of CPU fre- quency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power consumption, which is orders of magnitude smaller than the active power consumption. Consequently, power savings obtained by exclusively optimizing active power consumption (i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniquesâ that we report are orders of magnitude smaller than their simulation-based savings reported in the literature. Master of Science 2014-03-14T20:45:20Z 2014-03-14T20:45:20Z 2011-09-09 2011-09-12 2011-09-12 2011-09-12 Thesis etd-09122011-125316 http://hdl.handle.net/10919/35035 http://scholar.lib.vt.edu/theses/available/etd-09122011-125316/ Saha_S_T_2011.pdf In Copyright http://rightsstatements.org/vocab/InC/1.0/ application/pdf Virginia Tech |
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Dynamic Voltage and Frequency Scaling Real-Time Linux Saha, Sonal An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
description |
Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage-
ment technique, which aims to reduce the energy consumption of computing platforms by
dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS,
which reduces CPU energy consumption through DVFS, while at the same time ensures that
task time constraints are satisfied by constructing appropriate real-time task schedules. The
literature presents numerous RT-DVFS scheduling algorithms, which employ different tech-
niques to utilize the CPU idle time to scale the frequency. Many of these algorithms have
been experimentally studied through simulations, but have not been implemented on real
hardware platforms. Though simulation-based experimental studies can provide a first-order
understanding, implementation-based studies can reveal actual timeliness and energy con-
sumption behaviours. This is particularly important, when it is difficult to devise accurate
simulation models of hardware, which is increasingly the case with modern systems.
In this thesis, we study the timeliness and energy consumption behaviours of fourteen state-
of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware plat-
forms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others,
and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother-
board with the AMD Zacate processor. We implemented these schedulers in the ChronOS
real-time Linux kernel and measured their actual timeliness and energy behaviours under
a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-
intensive, and processor-underloaded and overloaded workloads.
Our studies reveal that measuring the CPU power consumption as the cube of CPU fre-
quency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power
consumption, which is orders of magnitude smaller than the active power consumption.
Consequently, power savings obtained by exclusively optimizing active power consumption
(i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest
frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power
consumption savings of the RT-DVFS techniquesâ that we report are orders of magnitude
smaller than their simulation-based savings reported in the literature. === Master of Science |
author2 |
Electrical and Computer Engineering |
author_facet |
Electrical and Computer Engineering Saha, Sonal |
author |
Saha, Sonal |
author_sort |
Saha, Sonal |
title |
An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
title_short |
An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
title_full |
An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
title_fullStr |
An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
title_full_unstemmed |
An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms |
title_sort |
experimental evaluation of real-time dvfs scheduling algorithms |
publisher |
Virginia Tech |
publishDate |
2014 |
url |
http://hdl.handle.net/10919/35035 http://scholar.lib.vt.edu/theses/available/etd-09122011-125316/ |
work_keys_str_mv |
AT sahasonal anexperimentalevaluationofrealtimedvfsschedulingalgorithms AT sahasonal experimentalevaluationofrealtimedvfsschedulingalgorithms |
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