A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform

A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform

This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex...

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Bibliographic Details
Main Author: Walters, Allison L.
Other Authors: Electrical Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
reconfigurable computing
digital signal processing
FIR filters
Online Access:http://hdl.handle.net/10919/35765
http://scholar.lib.vt.edu/theses/available/etd-11198-212219/
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spelling ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-357652020-09-29T05:43:25Z A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform Walters, Allison L. Electrical Engineering Athanas, Peter M. Jones, Mark T. Davis, Nathaniel J. IV reconfigurable computing digital signal processing FIR filters This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s. Master of Science 2014-03-14T20:48:09Z 2014-03-14T20:48:09Z 1998-01-30 1998-01-30 1998-02-23 1998-02-23 Thesis etd-11198-212219 http://hdl.handle.net/10919/35765 http://scholar.lib.vt.edu/theses/available/etd-11198-212219/ awalters.PDF In Copyright http://rightsstatements.org/vocab/InC/1.0/ application/pdf Virginia Tech
collection NDLTD
format Others
sources NDLTD
topic reconfigurable computing
digital signal processing
FIR filters
spellingShingle reconfigurable computing
digital signal processing
FIR filters
Walters, Allison L.
A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
description This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s. === Master of Science
author2 Electrical Engineering
author_facet Electrical Engineering
Walters, Allison L.
author Walters, Allison L.
author_sort Walters, Allison L.
title A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
title_short A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
title_full A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
title_fullStr A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
title_full_unstemmed A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
title_sort scaleable fir filter implementation using 32-bit floating-point complex arithmetic on a fpga base custom computing platform
publisher Virginia Tech
publishDate 2014
url http://hdl.handle.net/10919/35765
http://scholar.lib.vt.edu/theses/available/etd-11198-212219/
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AT waltersallisonl scaleablefirfilterimplementationusing32bitfloatingpointcomplexarithmeticonafpgabasecustomcomputingplatform
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