A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/35765 http://scholar.lib.vt.edu/theses/available/etd-11198-212219/ |