An improved chip-level test generation algorithm
An improved algorithm for the automatic generation of test vectors from chip-level descriptions written in VHDL is described. The method offers an order of magnitude speed improvement over earlier test generation algorithms. The algorithm accepts data flow circuit descriptions written in a subset of...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/43262 http://scholar.lib.vt.edu/theses/available/etd-06122010-020415/ |
