Shrinking the Cost of Telemetry Frame Synchronization
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada === To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Ver...
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ndltd-arizona.edu-oai-arizona.openrepository.com-10150-6116052016-06-08T03:01:39Z Shrinking the Cost of Telemetry Frame Synchronization Ghuman, Parminder Bennett, Toby Solomon, Jeff NASA, Goddard Space Flight Center RMS Technologies Inc. Frame Synchronization Telemetry Processing VLSI ASIC Low Cost International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device. 1995-11 text Proceedings 0884-5123 0074-9079 http://hdl.handle.net/10150/611605 http://arizona.openrepository.com/arizona/handle/10150/611605 International Telemetering Conference Proceedings en_US http://www.telemetry.org/ Copyright © International Foundation for Telemetering International Foundation for Telemetering |
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Frame Synchronization Telemetry Processing VLSI ASIC Low Cost |
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Frame Synchronization Telemetry Processing VLSI ASIC Low Cost Ghuman, Parminder Bennett, Toby Solomon, Jeff Shrinking the Cost of Telemetry Frame Synchronization |
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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada === To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device. |
author2 |
NASA, Goddard Space Flight Center |
author_facet |
NASA, Goddard Space Flight Center Ghuman, Parminder Bennett, Toby Solomon, Jeff |
author |
Ghuman, Parminder Bennett, Toby Solomon, Jeff |
author_sort |
Ghuman, Parminder |
title |
Shrinking the Cost of Telemetry Frame Synchronization |
title_short |
Shrinking the Cost of Telemetry Frame Synchronization |
title_full |
Shrinking the Cost of Telemetry Frame Synchronization |
title_fullStr |
Shrinking the Cost of Telemetry Frame Synchronization |
title_full_unstemmed |
Shrinking the Cost of Telemetry Frame Synchronization |
title_sort |
shrinking the cost of telemetry frame synchronization |
publisher |
International Foundation for Telemetering |
publishDate |
1995 |
url |
http://hdl.handle.net/10150/611605 http://arizona.openrepository.com/arizona/handle/10150/611605 |
work_keys_str_mv |
AT ghumanparminder shrinkingthecostoftelemetryframesynchronization AT bennetttoby shrinkingthecostoftelemetryframesynchronization AT solomonjeff shrinkingthecostoftelemetryframesynchronization |
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