LOW-POWER FAULT-TOLERANT MICROPROCESSOR-BASED DISTRIBUTED ARCHITECTURE FOR ON-BOARD SIGNAL PROCESSING
International Telemetering Conference Proceedings / October 24-27, 1983 / Sheraton-Harbor Island Hotel and Convention Center, San Diego, California === Numerous future space-based systems are being conceived that will require the on-board processing of a volume of data many orders of magnitude grea...
| Main Authors: | , , |
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| Other Authors: | |
| Language: | en_US |
| Published: |
International Foundation for Telemetering
1983
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| Online Access: | http://hdl.handle.net/10150/612436 http://arizona.openrepository.com/arizona/handle/10150/612436 |
| Summary: | International Telemetering Conference Proceedings / October 24-27, 1983 / Sheraton-Harbor Island Hotel and Convention Center, San Diego, California === Numerous future space-based systems are being conceived that will require the on-board
processing of a volume of data many orders of magnitude greater than the current state-ofthe-
art. Such systems must in addition be extremely low power and autonomously fault
recoverable. This paper describes a microprocessor-based distributed architecture that has
been evolving as a solution to this problem. This proposed architecture features three subarchitectures: synchronous pipeline, dedicated-channel microprocessor array, and multiplebus
oriented microcomputer array; as well as internal data compression, distributed control
and self testing, and a building block approach to system implementation. Emphasized is
the roll of microprocessors in this architecture and the challenge of reducing the overhead
required by fault-tolerant processing. |
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