New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits
abstract: Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis...
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ndltd-asu.edu-item-274682018-06-22T03:05:43Z New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits abstract: Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects. The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI. Dissertation/Thesis Padala, Sudheer (Author) Barnaby, Hugh (Advisor) Bakkaloglu, Bertan (Committee member) Kitchen, Jennifer (Committee member) Arizona State University (Publisher) Electrical engineering eng 75 pages Masters Thesis Electrical Engineering 2014 Masters Thesis http://hdl.handle.net/2286/R.I.27468 http://rightsstatements.org/vocab/InC/1.0/ All Rights Reserved 2014 |
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NDLTD |
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English |
format |
Dissertation |
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Electrical engineering |
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Electrical engineering New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
description |
abstract: Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI. === Dissertation/Thesis === Masters Thesis Electrical Engineering 2014 |
author2 |
Padala, Sudheer (Author) |
author_facet |
Padala, Sudheer (Author) |
title |
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
title_short |
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
title_full |
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
title_fullStr |
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
title_full_unstemmed |
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits |
title_sort |
new model for simulating impact of negative bias temperature instability (nbti) in cmos circuits |
publishDate |
2014 |
url |
http://hdl.handle.net/2286/R.I.27468 |
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1718700615883816960 |