Exploiting instruction-level parallelism in superscalar architecture

Bibliographic Details
Main Author:	Collins, Roger
Published:	University of Hertfordshire 1995
Subjects:	005 Scheduling code
Online Access:	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.283865

id	ndltd-bl.uk-oai-ethos.bl.uk-283865
record_format	oai_dc
spelling	ndltd-bl.uk-oai-ethos.bl.uk-2838652015-03-19T04:43:11ZExploiting instruction-level parallelism in superscalar architectureCollins, Roger1995005Scheduling codeUniversity of Hertfordshirehttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.283865Electronic Thesis or Dissertation
collection	NDLTD
sources	NDLTD
topic	005 Scheduling code
spellingShingle	005 Scheduling code Collins, Roger Exploiting instruction-level parallelism in superscalar architecture
author	Collins, Roger
author_facet	Collins, Roger
author_sort	Collins, Roger
title	Exploiting instruction-level parallelism in superscalar architecture
title_short	Exploiting instruction-level parallelism in superscalar architecture
title_full	Exploiting instruction-level parallelism in superscalar architecture
title_fullStr	Exploiting instruction-level parallelism in superscalar architecture
title_full_unstemmed	Exploiting instruction-level parallelism in superscalar architecture
title_sort	exploiting instruction-level parallelism in superscalar architecture
publisher	University of Hertfordshire
publishDate	1995
url	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.283865
work_keys_str_mv	AT collinsroger exploitinginstructionlevelparallelisminsuperscalararchitecture
_version_	1716737988199710720

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