Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces

Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces

Bibliographic Details
Main Author: Cevik, Ulus
Published: University of Sussex 1996
Subjects:
621.3994
Field programmable gate array
Online Access:http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.321348
id ndltd-bl.uk-oai-ethos.bl.uk-321348
record_format oai_dc
spelling ndltd-bl.uk-oai-ethos.bl.uk-3213482015-04-03T03:20:33ZDesign of an FPGA based parallel architecture processor for displaying CSG volumes and surfacesCevik, Ulus1996621.3994Field programmable gate arrayUniversity of Sussexhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.321348Electronic Thesis or Dissertation
collection NDLTD
sources NDLTD
topic 621.3994
Field programmable gate array
spellingShingle 621.3994
Field programmable gate array
Cevik, Ulus
Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
author Cevik, Ulus
author_facet Cevik, Ulus
author_sort Cevik, Ulus
title Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
title_short Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
title_full Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
title_fullStr Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
title_full_unstemmed Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces
title_sort design of an fpga based parallel architecture processor for displaying csg volumes and surfaces
publisher University of Sussex
publishDate 1996
url http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.321348
work_keys_str_mv AT cevikulus designofanfpgabasedparallelarchitectureprocessorfordisplayingcsgvolumesandsurfaces
_version_ 1716799936670990336

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