Adaptive adjustment filter techniques applied to digital data receivers for telephone channels, HF & mobile radio links

The thesis investigates techniques for the adjustment of pre-detection filters employed by high speed serial digital modems operating over both time-invariant and timevarying channels. Various techniques for the adjustment of these pre-detection filters have been considered in previous investigation...

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Bibliographic Details
Main Author: Tsabieris, Nikos I.
Published: Loughborough University 1996
Subjects:
Online Access:http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558028
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Summary:The thesis investigates techniques for the adjustment of pre-detection filters employed by high speed serial digital modems operating over both time-invariant and timevarying channels. Various techniques for the adjustment of these pre-detection filters have been considered in previous investigations. The more recent ones enable such filters to be adjusted in a simple and accurate way using an estimate of the sampled impulse response of the linear baseband channel, together with a prior knowledge of the roots that lie outside the unit circle in the z-plane. A root finding algorithm is an integral part of these techniques. Algorithms for the location of the required roots are presented here, and compared with previous ones in an attempt to optimise the operational speed and accuracy of the adjustment of these filters. Alternative algorithm have also been considered, that operate directly on the sampled impulse response of the linear baseband channel, without the need for locating any roots, thus enabling a faster and more accurate adjustment of the pre-detection filter. The relative performances of all the algorithms are then evaluated over different telephone channels, at transmission rates of 9600 and 19200 bits/sec. The algorithms are also tested over fading channels (such as HF radio links), so as to select the one which offers the best compromise between performance and complexity for hardware implementation. Finally, various aspects of the hardware implementation of the selected algorithm have been considered.