Reconfiguration of field programmable logic in embedded systems

• Main Author: Kennedy, Irwin O.
• Published: University of Edinburgh 2005
• Subjects: 004
• Online Access: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653301

This thesis proposes a systematic approach to reconfigurable realtime system design. It exploits static and medium frequency reconfiguration by exploiting inter-task mutually exclusive resource usage. It exploits high frequency reconfiguration through data-folding specialisation techniques. A procedure for creating parameterised designs that approach minimal coverage of all possible system requirements is described. A runtime framework based upon a regularly occurring system-wide pause of execution is described. A large case study of the design approach and runtime framework is presented and compared with the static equivalent. The case study system is a commercial Universal Mobile Telecommunications System (UMTS) physical layer processing engine. Equations describing the logic gate and memory requirements of the commercial ASIC design are extracted and used to estimate resource requirements of a low-medium frequency reconfigurable solution. A detailed investigation of very rapid reconfiguration is carried out on a large circuit block. Good logic and memory resource requirement reduction is shown to be possible. A complementary FPGA reconfiguration architecture is presented. It provides the ability to tradeoff time and space according to the reconfiguration speed requirements of an application domain. A number of configuration compression schemes are investigated.  In addition to an excellent compression ratio they are shown to be highly parallelisable and scalable, unlike previous approaches.