Hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnections.

• Other Authors: Lo, Wing-yee.
• Format: Others
• Language: English
• Published: Chinese University of Hong Kong 1994
• Subjects: Gate array circuits; Programmable logic devices; Pragrammable array logic; Electronic digital computers > Circuits > Design and construction
• Online Access: http://library.cuhk.edu.hk/record=b5888211; http://repository.lib.cuhk.edu.hk/en/item/cuhk-318185

by Lo Wing-yee. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. === Includes bibliographical references (leaves vii-ix). === ABSTRACT --- p.i === LIST OF TABLES --- p.iv === LIST OF FIGURES --- p.v === Chapter 1. --- INTRODUCTION --- p.1 === Chapter 1.1 --- Traditional Design Prototyping --- p.1 === Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2 === Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5 === Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6 === Chapter 2. --- HARDWARE DESIGNS --- p.9 === Chapter 2.1 --- Bus Interconnection --- p.9 === Chapter 2.1.1 --- Fixed buses --- p.9 === Chapter 2.1.2 --- Programmable buses --- p.12 === Chapter 2.2 --- Architectural Features --- p.15 === Chapter 2.2.1 --- Field programmable gate array --- p.15 === Chapter 2.2.2 --- Microprocessor --- p.15 === Chapter 2.2.3 --- Memory --- p.16 === Chapter 2.2.4 --- Buffers --- p.18 === Chapter 3. --- SOFTWARE TOOLS --- p.20 === Chapter 3.1 --- Critical Path Analysis --- p.20 === Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21 === Chapter 3.1.2 --- Computation time --- p.21 === Chapter 3.2 --- Circuit Partitioning --- p.23 === Chapter 3.2.1 --- Partitioning algorithm --- p.24 === Chapter 3.2.2 --- Effects of partitioning --- p.36 === Chapter 3.2.3 --- Partitioning parameters --- p.38 === Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39 === Chapter 3.3 --- IO Assignments --- p.40 === Chapter 3.3.1 --- Connect 4 FPGAs --- p.40 === Chapter 3.3.2 --- Connect 3 FPGAs --- p.42 === Chapter 3.3.3 --- Connect 2 FPGAs --- p.44 === Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47 === Chapter 3.4 --- Other Tools --- p.48 === Chapter 4. --- STRUCTURE ANALYSIS --- p.49 === Chapter 5. --- RESULTS --- p.52 === Chapter 6. --- FUTURE DIRECTION --- p.73 === Chapter 6.1 --- Other Possible Configurations --- p.73 === Chapter 6.2 --- Programmable Interconnection --- p.73 === Chapter 6.3 --- Expandability of UPB --- p.74 === Chapter 7. --- CONCLUSION --- p.75 === BIBLIOGRAPHY --- p.vii === APPENDICES --- p.x