Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes.
by Stephen Siu-ming Wong. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. === Includes bibliographical references (leaves 164-170). === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Cache Memory --- p.2 === Chapter 1.2 --- System Performance --- p.3 === Chapter 1.3 --- Cache...
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Chinese University of Hong Kong
1996
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Online Access: | http://library.cuhk.edu.hk/record=b5895702 http://repository.lib.cuhk.edu.hk/en/item/cuhk-321556 |
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Cache memory Memory management (Computer science) Random access memory |
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Cache memory Memory management (Computer science) Random access memory Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
description |
by Stephen Siu-ming Wong. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. === Includes bibliographical references (leaves 164-170). === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Cache Memory --- p.2 === Chapter 1.2 --- System Performance --- p.3 === Chapter 1.3 --- Cache Performance --- p.3 === Chapter 1.4 --- Cache Prefetching --- p.5 === Chapter 1.5 --- Organization of Dissertation --- p.7 === Chapter 2 --- Related Work --- p.8 === Chapter 2.1 --- Memory Hierarchy --- p.8 === Chapter 2.2 --- Cache Memory Management --- p.10 === Chapter 2.2.1 --- Configuration --- p.10 === Chapter 2.2.2 --- Replacement Algorithms --- p.13 === Chapter 2.2.3 --- Write Back Policies --- p.15 === Chapter 2.2.4 --- Cache Miss Types --- p.16 === Chapter 2.2.5 --- Prefetching --- p.17 === Chapter 2.3 --- Locality --- p.18 === Chapter 2.3.1 --- Spatial vs. Temporal --- p.18 === Chapter 2.3.2 --- Instruction Cache vs. Data Cache --- p.20 === Chapter 2.4 --- Why Not a Large L1 Cache? --- p.26 === Chapter 2.4.1 --- Critical Time Path --- p.26 === Chapter 2.4.2 --- Hardware Cost --- p.27 === Chapter 2.5 --- Trend to have L2 Cache On Chip --- p.28 === Chapter 2.5.1 --- Examples --- p.29 === Chapter 2.5.2 --- Dedicated L2 Bus --- p.31 === Chapter 2.6 --- Hardware Prefetch Algorithms --- p.32 === Chapter 2.6.1 --- One Block Look-ahead --- p.33 === Chapter 2.6.2 --- Chen's RPT & similar algorithms --- p.34 === Chapter 2.7 --- Software Based Prefetch Algorithm --- p.38 === Chapter 2.7.1 --- Prefetch Instruction --- p.38 === Chapter 2.8 --- Hybrid Prefetch Algorithm --- p.40 === Chapter 2.8.1 --- Stride CAM Prefetching --- p.40 === Chapter 3 --- Simulator --- p.43 === Chapter 3.1 --- Multi-level Memory Hierarchy Simulator --- p.43 === Chapter 3.1.1 --- Multi-level Memory Support --- p.45 === Chapter 3.1.2 --- Non-blocking Cache --- p.45 === Chapter 3.1.3 --- Cycle-by-cycle Simulation --- p.47 === Chapter 3.1.4 --- Cache Prefetching Support --- p.47 === Chapter 4 --- Proposed Algorithms --- p.48 === Chapter 4.1 --- SIRPA --- p.48 === Chapter 4.1.1 --- Rationale --- p.48 === Chapter 4.1.2 --- Architecture Model --- p.50 === Chapter 4.2 --- Line Concept --- p.56 === Chapter 4.2.1 --- Rationale --- p.56 === Chapter 4.2.2 --- "Improvement Over ""Pure"" Algorithm" --- p.57 === Chapter 4.2.3 --- Architectural Model --- p.59 === Chapter 4.3 --- Combined L1-L2 Cache Management --- p.62 === Chapter 4.3.1 --- Rationale --- p.62 === Chapter 4.3.2 --- Feasibility --- p.63 === Chapter 4.4 --- Combine SIRPA with Default Prefetch --- p.66 === Chapter 4.4.1 --- Rationale --- p.67 === Chapter 4.4.2 --- Improvement Over “Pure´ح Algorithm --- p.69 === Chapter 4.4.3 --- Architectural Model --- p.70 === Chapter 5 --- Results --- p.73 === Chapter 5.1 --- Benchmarks Used --- p.73 === Chapter 5.1.1 --- SPEC92int and SPEC92fp --- p.75 === Chapter 5.2 --- Configurations Tested --- p.79 === Chapter 5.2.1 --- Prefetch Algorithms --- p.79 === Chapter 5.2.2 --- Cache Sizes --- p.80 === Chapter 5.2.3 --- Cache Block Sizes --- p.81 === Chapter 5.2.4 --- Cache Set Associativities --- p.81 === Chapter 5.2.5 --- "Bus Width, Speed and Other Parameters" --- p.81 === Chapter 5.3 --- Validity of Results --- p.83 === Chapter 5.3.1 --- Total Instructions and Cycles --- p.83 === Chapter 5.3.2 --- Total Reference to Caches --- p.84 === Chapter 5.4 --- Overall MCPI Comparison --- p.86 === Chapter 5.4.1 --- Cache Size Effect --- p.87 === Chapter 5.4.2 --- Cache Block Size Effect --- p.91 === Chapter 5.4.3 --- Set Associativity Effect --- p.101 === Chapter 5.4.4 --- Hardware Prefetch Algorithms --- p.108 === Chapter 5.4.5 --- Software Based Prefetch Algorithms --- p.119 === Chapter 5.5 --- L2 Cache & Main Memory MCPI Comparison --- p.127 === Chapter 5.5.1 --- Cache Size Effect --- p.130 === Chapter 5.5.2 --- Cache Block Size Effect --- p.130 === Chapter 5.5.3 --- Set Associativity Effect --- p.143 === Chapter 6 --- Conclusion --- p.154 === Chapter 7 --- Future Directions --- p.157 === Chapter 7.1 --- Prefetch Buffer --- p.157 === Chapter 7.2 --- Dissimilar L1-L2 Management --- p.158 === Chapter 7.3 --- Combined LRU/MRU Replacement Policy --- p.160 === Chapter 7.4 --- N Loops Look-ahead --- p.163 |
author2 |
Wong, Stephen Siu-ming. |
author_facet |
Wong, Stephen Siu-ming. |
title |
Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
title_short |
Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
title_full |
Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
title_fullStr |
Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
title_full_unstemmed |
Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
title_sort |
unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. |
publisher |
Chinese University of Hong Kong |
publishDate |
1996 |
url |
http://library.cuhk.edu.hk/record=b5895702 http://repository.lib.cuhk.edu.hk/en/item/cuhk-321556 |
_version_ |
1718980140439961600 |
spelling |
ndltd-cuhk.edu.hk-oai-cuhk-dr-cuhk_3215562019-02-19T03:57:01Z Unified on-chip multi-level cache management scheme using processor opcodes and addressing modes. Cache memory Memory management (Computer science) Random access memory by Stephen Siu-ming Wong. Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. Includes bibliographical references (leaves 164-170). Chapter 1 --- Introduction --- p.1 Chapter 1.1 --- Cache Memory --- p.2 Chapter 1.2 --- System Performance --- p.3 Chapter 1.3 --- Cache Performance --- p.3 Chapter 1.4 --- Cache Prefetching --- p.5 Chapter 1.5 --- Organization of Dissertation --- p.7 Chapter 2 --- Related Work --- p.8 Chapter 2.1 --- Memory Hierarchy --- p.8 Chapter 2.2 --- Cache Memory Management --- p.10 Chapter 2.2.1 --- Configuration --- p.10 Chapter 2.2.2 --- Replacement Algorithms --- p.13 Chapter 2.2.3 --- Write Back Policies --- p.15 Chapter 2.2.4 --- Cache Miss Types --- p.16 Chapter 2.2.5 --- Prefetching --- p.17 Chapter 2.3 --- Locality --- p.18 Chapter 2.3.1 --- Spatial vs. Temporal --- p.18 Chapter 2.3.2 --- Instruction Cache vs. Data Cache --- p.20 Chapter 2.4 --- Why Not a Large L1 Cache? --- p.26 Chapter 2.4.1 --- Critical Time Path --- p.26 Chapter 2.4.2 --- Hardware Cost --- p.27 Chapter 2.5 --- Trend to have L2 Cache On Chip --- p.28 Chapter 2.5.1 --- Examples --- p.29 Chapter 2.5.2 --- Dedicated L2 Bus --- p.31 Chapter 2.6 --- Hardware Prefetch Algorithms --- p.32 Chapter 2.6.1 --- One Block Look-ahead --- p.33 Chapter 2.6.2 --- Chen's RPT & similar algorithms --- p.34 Chapter 2.7 --- Software Based Prefetch Algorithm --- p.38 Chapter 2.7.1 --- Prefetch Instruction --- p.38 Chapter 2.8 --- Hybrid Prefetch Algorithm --- p.40 Chapter 2.8.1 --- Stride CAM Prefetching --- p.40 Chapter 3 --- Simulator --- p.43 Chapter 3.1 --- Multi-level Memory Hierarchy Simulator --- p.43 Chapter 3.1.1 --- Multi-level Memory Support --- p.45 Chapter 3.1.2 --- Non-blocking Cache --- p.45 Chapter 3.1.3 --- Cycle-by-cycle Simulation --- p.47 Chapter 3.1.4 --- Cache Prefetching Support --- p.47 Chapter 4 --- Proposed Algorithms --- p.48 Chapter 4.1 --- SIRPA --- p.48 Chapter 4.1.1 --- Rationale --- p.48 Chapter 4.1.2 --- Architecture Model --- p.50 Chapter 4.2 --- Line Concept --- p.56 Chapter 4.2.1 --- Rationale --- p.56 Chapter 4.2.2 --- "Improvement Over ""Pure"" Algorithm" --- p.57 Chapter 4.2.3 --- Architectural Model --- p.59 Chapter 4.3 --- Combined L1-L2 Cache Management --- p.62 Chapter 4.3.1 --- Rationale --- p.62 Chapter 4.3.2 --- Feasibility --- p.63 Chapter 4.4 --- Combine SIRPA with Default Prefetch --- p.66 Chapter 4.4.1 --- Rationale --- p.67 Chapter 4.4.2 --- Improvement Over “Pure´ح Algorithm --- p.69 Chapter 4.4.3 --- Architectural Model --- p.70 Chapter 5 --- Results --- p.73 Chapter 5.1 --- Benchmarks Used --- p.73 Chapter 5.1.1 --- SPEC92int and SPEC92fp --- p.75 Chapter 5.2 --- Configurations Tested --- p.79 Chapter 5.2.1 --- Prefetch Algorithms --- p.79 Chapter 5.2.2 --- Cache Sizes --- p.80 Chapter 5.2.3 --- Cache Block Sizes --- p.81 Chapter 5.2.4 --- Cache Set Associativities --- p.81 Chapter 5.2.5 --- "Bus Width, Speed and Other Parameters" --- p.81 Chapter 5.3 --- Validity of Results --- p.83 Chapter 5.3.1 --- Total Instructions and Cycles --- p.83 Chapter 5.3.2 --- Total Reference to Caches --- p.84 Chapter 5.4 --- Overall MCPI Comparison --- p.86 Chapter 5.4.1 --- Cache Size Effect --- p.87 Chapter 5.4.2 --- Cache Block Size Effect --- p.91 Chapter 5.4.3 --- Set Associativity Effect --- p.101 Chapter 5.4.4 --- Hardware Prefetch Algorithms --- p.108 Chapter 5.4.5 --- Software Based Prefetch Algorithms --- p.119 Chapter 5.5 --- L2 Cache & Main Memory MCPI Comparison --- p.127 Chapter 5.5.1 --- Cache Size Effect --- p.130 Chapter 5.5.2 --- Cache Block Size Effect --- p.130 Chapter 5.5.3 --- Set Associativity Effect --- p.143 Chapter 6 --- Conclusion --- p.154 Chapter 7 --- Future Directions --- p.157 Chapter 7.1 --- Prefetch Buffer --- p.157 Chapter 7.2 --- Dissimilar L1-L2 Management --- p.158 Chapter 7.3 --- Combined LRU/MRU Replacement Policy --- p.160 Chapter 7.4 --- N Loops Look-ahead --- p.163 Chinese University of Hong Kong Wong, Stephen Siu-ming. Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. 1996 Text bibliography print xii, 170 leaves : ill. ; 30 cm. cuhk:321556 http://library.cuhk.edu.hk/record=b5895702 eng Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) http://repository.lib.cuhk.edu.hk/en/islandora/object/cuhk%3A321556/datastream/TN/view/Unified%20on-chip%20multi-level%20cache%20management%20scheme%20using%20processor%20opcodes%20and%20addressing%20modes.jpghttp://repository.lib.cuhk.edu.hk/en/item/cuhk-321556 |