Asynchronous memory design.

• Other Authors: Sit, Vincent Wing-Yun.
• Format: Others
• Language: English; Chinese
• Published: 1998
• Subjects: Asynchronous transfer mode; Random access memory
• Online Access: http://library.cuhk.edu.hk/record=b5889510; http://repository.lib.cuhk.edu.hk/en/item/cuhk-322352

by Vincent Wing-Yun Sit. === Thesis submitted in: June 1997. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. === Includes bibliographical references (leaves 1-4 (3rd gp.)). === Abstract also in Chinese. === TABLE OF CONTENTS === LIST OF FIGURES === LIST OF TABLES === ACKNOWLEDGEMENTS === ABSTRACT === Chapter 1. --- INTRODUCTION --- p.1 === Chapter 1.1 --- ASYNCHRONOUS DESIGN --- p.2 === Chapter 1.1.1 --- POTENTIAL ADVANTAGES --- p.2 === Chapter 1.1.2 --- DESIGN METHODOLOGIES --- p.2 === Chapter 1.1.3 --- SYSTEM CHARACTERISTICS --- p.3 === Chapter 1.2 --- ASYNCHRONOUS MEMORY --- p.5 === Chapter 1.2.1 --- MOTIVATION --- p.5 === Chapter 1.2.2 --- DEFINITION --- p.9 === Chapter 1.3 --- PROPOSED MEMORY DESIGN --- p.10 === Chapter 1.3.1 --- CONTROL INTERFACE --- p.10 === Chapter 1.3.2 --- OVERVIEW --- p.11 === Chapter 1.3.3 --- HANDSHAKE CONTROL PROTOCOL --- p.13 === Chapter 2. --- THEORY --- p.16 === Chapter 2.1 --- VARIABLE BIT LINE LOAD --- p.17 === Chapter 2.1.1 --- DEFINITION --- p.17 === Chapter 2.1.2 --- ADVANTAGE --- p.17 === Chapter 2.2 --- CURRENT SENSING COMPLETION DETECTION --- p.18 === Chapter 2.2.1 --- BLOCK DIAGRAM --- p.19 === Chapter 2.2.2 --- GENERAL LSD CURRENT SENSOR --- p.21 === Chapter 2.2.3 --- CMOS LSD CURRENT SENSOR --- p.23 === Chapter 2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.28 === Chapter 2.3.1 --- DATA READING IN MEMORY CIRCUIT --- p.29 === Chapter 2.3.2 --- BLOCK DIAGRAM --- p.30 === Chapter 2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.32 === Chapter 2.4.1 --- ADVANTAGE --- p.32 === Chapter 2.4.2 --- BLOCK DIAGRAM --- p.33 === Chapter 3. --- IMPLEMENTATION --- p.35 === Chapter 3.1 --- 1M-BIT SRAM FRAMEWORK --- p.36 === Chapter 3.1.1 --- INTRODUCTION --- p.36 === Chapter 3.1.2 --- FRAMEWORK --- p.36 === Chapter 3.2 --- CONTROL CIRCUIT --- p.40 === Chapter 3.2.1 --- CONTROL SIGNALS --- p.40 === Chapter 3.2.1.1 --- EXTERNAL CONTROL SIGNALS --- p.40 === Chapter 3.2.1.2 --- INTERNAL CONTROL SIGNALS --- p.41 === Chapter 3.2.2 --- READ / WRITE STATE TRANSITION GRAPHS --- p.42 === Chapter 3.2.3 --- IMPLEMENTATION --- p.43 === Chapter 3.3 --- BIT LINE SEGMENTATION --- p.45 === Chapter 3.3.1 --- FOUR REGIONS SEGMENTATION --- p.46 === Chapter 3.3.2 --- OPERATION --- p.50 === Chapter 3.3.3 --- MEMORY CELL --- p.51 === Chapter 3.4 --- CURRENT SENSING COMPLETION DETECTION --- p.52 === Chapter 3.4.1 --- ONE BIT DATA BUS --- p.53 === Chapter 3.4.2 --- EIGHT BITS DATA BUS --- p.55 === Chapter 3.5 --- VOLTAGE SENSING COMPLETION DETECTION --- p.57 === Chapter 3.5.1 --- ONE BIT DATA BUS --- p.57 === Chapter 3.5.2 --- EIGHT BITS DATA BUS --- p.59 === Chapter 3.6 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.60 === Chapter 4. --- SIMULATION --- p.63 === Chapter 4.1 --- SIMULATION ENVIRONMENT --- p.64 === Chapter 4.1.1 --- SIMULATION PARAMETERS --- p.64 === Chapter 4.1.2 --- MEMORY TIMING SPECIFICATIONS --- p.64 === Chapter 4.1.3 --- BIT LINE LOAD DETERMINATION --- p.67 === Chapter 4.2 --- BENCHMARK SIMULATION --- p.69 === Chapter 4.2.1 --- CIRCUIT SCHEMATIC --- p.69 === Chapter 4.2.2 --- RESULTS --- p.71 === Chapter 4.3 --- CURRENT SENSING COMPLETION DETECTION --- p.73 === Chapter 4.3.1 --- CIRCUIT SCHEMATIC --- p.73 === Chapter 4.3.2 --- SENSE AMPLIFIER CURRENT CHARACTERISTICS --- p.75 === Chapter 4.3.3 --- RESULTS --- p.76 === Chapter 4.3.4 --- OBSERVATIONS --- p.80 === Chapter 4.4 --- VOLTAGE SENSING COMPLETION DETECTION --- p.82 === Chapter 4.4.1 --- CIRCUIT SCHEMATIC --- p.82 === Chapter 4.4.2 --- RESULTS --- p.83 === Chapter 4.5 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.89 === Chapter 4.5.1 --- CIRCUIT SCHEMATIC --- p.89 === Chapter 4.5.2 --- RESULTS --- p.90 === Chapter 5. --- TESTING --- p.97 === Chapter 5.1 --- TEST CHIP DESIGN --- p.98 === Chapter 5.1.1 --- BLOCK DIAGRAM --- p.98 === Chapter 5.1.2 --- SCHEMATIC --- p.100 === Chapter 5.1.3 --- LAYOUT --- p.102 === Chapter 5.2 --- HSPICE POST-LAYOUT SIMULATION RESULTS --- p.104 === Chapter 5.2.1 --- GRAPHICAL RESULTS --- p.105 === Chapter 5.2.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.108 === Chapter 5.2.3 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.114 === Chapter 5.3 --- MEASUREMENTS --- p.117 === Chapter 5.3.1 --- LOGIC RESULTS --- p.118 === Chapter 5.3.1.1 --- METHOD --- p.118 === Chapter 5.3.1.2 --- RESULTS --- p.118 === Chapter 5.3.2 --- TIMING RESULTS --- p.119 === Chapter 5.3.2.1 --- METHOD --- p.119 === Chapter 5.3.2.2 --- GRAPHICAL RESULTS --- p.121 === Chapter 5.3.2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.123 === Chapter 5.3.2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.125 === Chapter 6. --- DISCUSSION --- p.127 === Chapter 6.1 --- CURRENT SENSING COMPLETION DETECTION --- p.128 === Chapter 6.1.1 --- COMMENTS AND CONCLUSION --- p.128 === Chapter 6.1.2 --- SUGGESTION --- p.128 === Chapter 6.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.129 === Chapter 6.2.1 --- RESULTS COMPARISON --- p.129 === Chapter 6.2.1.1 --- GENERAL --- p.129 === Chapter 6.2.1.2 --- BIT LINE LOAD --- p.132 === Chapter 6.2.1.3 --- BIT LINE SEGMENTATION --- p.133 === Chapter 6.2.2 --- RESOURCE CONSUMPTION --- p.133 === Chapter 6.2.2.1 --- AREA --- p.133 === Chapter 6.2.2.2 --- POWER --- p.134 === Chapter 6.2.3 --- COMMENTS AND CONCLUSION --- p.134 === Chapter 6.3 --- MULTIPLE DELAY COMPLETION GENERATION --- p.135 === Chapter 6.3.1 --- RESULTS COMPARISON --- p.135 === Chapter 6.3.1.1 --- GENERAL --- p.135 === Chapter 6.3.1.2 --- BIT LINE LOAD --- p.136 === Chapter 6.3.1.3 --- BIT LINE SEGMENTATION --- p.137 === Chapter 6.3.2 --- RESOURCE CONSUMPTION --- p.138 === Chapter 6.3.2.1 --- AREA --- p.138 === Chapter 6.3.2.2 --- POWER --- p.138 === Chapter 6.3.3 --- COMMENTS AND CONCLUSION --- p.138 === Chapter 6.4 --- GENERAL COMMENTS --- p.139 === Chapter 6.4.1 --- COMPARISON OF THE THREE TECHNIQUES --- p.139 === Chapter 6.4.2 --- BIT LINE SEGMENTATION --- p.141 === Chapter 6.5 --- APPLICATION --- p.142 === Chapter 6.6 --- FURTHER DEVELOPMENTS --- p.144 === Chapter 6.6.1 --- INTERACE WITH TWO-PHASE HCP --- p.144 === Chapter 6.6.2 --- DATA BUS EXPANSION --- p.146 === Chapter 6.6.3 --- SPEED OPTIMIZATION --- p.147 === Chapter 6.6.4 --- MODIFIED WRITE COMPLETION METHOD --- p.150 === Chapter 7. --- CONCLUSION --- p.152 === Chapter 7.1 --- PROBLEM DEFINITION --- p.152 === Chapter 7.2 --- IMPLEMENTATION --- p.152 === Chapter 7.3 --- EVALUATION --- p.153 === Chapter 7.4 --- COMMENTS AND SUGGESTIONS --- p.155 === Chapter 8. --- REFERENCES --- p.R-l === Chapter 9. --- APPENDIX --- p.A-l === Chapter 9.1 --- HSPICE SIMULATION PARAMETERS --- p.A-l === Chapter 9.1.1 --- TYPICAL SIMULATION CONDITION --- p.A-l === Chapter 9.1.2 --- FAST SIMULATION CONDITION --- p.A-3 === Chapter 9.1.3 --- SLOW SIMULATION CONDITION --- p.A-4 === Chapter 9.2 --- SRAM CELL LAYOUT AND NETLIST --- p.A-5 === Chapter 9.3 --- TEST CHIP SPECIFICATIONS --- p.A-8 === Chapter 9.3.1 --- GENERAL SPECIFICATIONS --- p.A-8 === Chapter 9.3.2 --- PIN ASSIGNMENT --- p.A-9 === Chapter 9.3.3 --- TIMING DIAGRAMS AND SPECIFICATIONS --- p.A-10 === Chapter 9.3.4 --- SCHEMATICS AND LAYOUTS --- p.A-11 === Chapter 9.3.4.1 --- STANDARD MEMORY COMPONENTS --- p.A-12 === Chapter 9.3.4.2 --- DVSCD AND MDCG COMPONENTS --- p.A-20 === Chapter 9.3.5 --- MICROPHOTOGRAPH --- p.A-25