Test architecture design and optimization for three-dimensional system-on-chips.

• Other Authors: Jiang, Li.
• Format: Others
• Language: English; Chinese
• Published: 2010
• Subjects: Systems on a chip > Testing; Integrated circuits > Design and construction; Three-dimensional display systems
• Online Access: http://library.cuhk.edu.hk/record=b5894366; http://repository.lib.cuhk.edu.hk/en/item/cuhk-327136

Jiang, Li. === "October 2010." === Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. === Includes bibliographical references (leaves 71-76). === Abstracts in English and Chinese. === Abstract --- p.i === Acknowledgement --- p.ii === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Three Dimensional Integrated Circuit --- p.1 === Chapter 1.1.1 --- 3D ICs --- p.1 === Chapter 1.1.2 --- Manufacture --- p.3 === Chapter 1.2 --- Test Architecture Design and Optimization for SoCs --- p.4 === Chapter 1.2.1 --- Test Wrapper --- p.4 === Chapter 1.2.2 --- Test Access Mechanism --- p.6 === Chapter 1.2.3 --- Test Architecture Optimization and Test Scheduling --- p.7 === Chapter 1.3 --- Thesis Motivation and Organization --- p.9 === Chapter 2 --- On Test Time and Routing Cost --- p.12 === Chapter 2.1 --- Introduction --- p.12 === Chapter 2.2 --- Preliminaries and Motivation --- p.13 === Chapter 2.3 --- Problem Formulation --- p.17 === Chapter 2.3.1 --- Test Cost Model --- p.17 === Chapter 2.3.2 --- Routing Model --- p.17 === Chapter 2.3.3 --- Problem Definition --- p.19 === Chapter 2.4 --- Proposed Algorithm --- p.22 === Chapter 2.4.1 --- Outline of The Proposed Algorithm --- p.22 === Chapter 2.4.2 --- SA-Based Core Assignment --- p.24 === Chapter 2.4.3 --- Heuristic-Based TAM Width Allocation --- p.25 === Chapter 2.4.4 --- Fast routing Heuristic --- p.28 === Chapter 2.5 --- Experiments --- p.29 === Chapter 2.5.1 --- Experimental Setup --- p.29 === Chapter 2.5.2 --- Experimental Results --- p.31 === Chapter 2.6 --- Conclusion --- p.34 === Chapter 3 --- Pre-bond-Test-Pin Constrained Test Wire Sharing --- p.37 === Chapter 3.1 --- Introduction --- p.37 === Chapter 3.2 --- Preliminaries and Motivation --- p.38 === Chapter 3.2.1 --- Prior Work in SoC Testing --- p.38 === Chapter 3.2.2 --- Prior Work in Testing 3D ICs --- p.39 === Chapter 3.2.3 --- Test-Pin-Count Constraint in 3D IC Pre-Bond Testing --- p.40 === Chapter 3.2.4 --- Motivation --- p.41 === Chapter 3.3 --- Problem Formulation --- p.43 === Chapter 3.3.1 --- Test Architecture Design under Pre-Bond Test-Pin-Count Constraint --- p.44 === Chapter 3.3.2 --- Thermal-aware Test Scheduling for Post-Bond Test --- p.45 === Chapter 3.4 --- Layout-Driven Test Architecture Design and Optimization --- p.46 === Chapter 3.4.1 --- Scheme 1: TAM Wire Reuse with Fixed Test Architectures --- p.46 === Chapter 3.4.2 --- Scheme 2: TAM Wire Reuse with Flexible Pre-bond Test Architecture --- p.52 === Chapter 3.5 --- Thermal-Aware Test Scheduling for Post-Bond Test --- p.53 === Chapter 3.5.1 --- Thermal Cost Function --- p.54 === Chapter 3.5.2 --- Test Scheduling Algorithm --- p.55 === Chapter 3.6 --- Experimental Results --- p.56 === Chapter 3.6.1 --- Experimental Setup --- p.56 === Chapter 3.6.2 --- Results and Discussion --- p.58 === Chapter 3.7 --- Conclusion --- p.59 === Chapter 3.8 --- Acknowledgement --- p.60 === Chapter 4 --- Conclusion and Future Work --- p.69 === Bibliography --- p.70