Testing and evaluation of the configurable fault tolerant processor (CFTP) for space-based application

• Main Author: Hulme, Charles A.
• Other Authors: Loomis, Herschel H., Jr.
• Published: Monterey, California. Naval Postgraduate School 2012
• Online Access: http://hdl.handle.net/10945/6189

Approved for public release; distribution is unlimited === With the complexity of digital systems, reliability considerations are important. In many digital systems it is desirable to con-tinuously monitor, exercise and test the system in order to determine whether the system is performing as desired. Such moni-toring may enable automatic detection of failures via periodic testing or through the use of codes and checking circuits (e.g., built-in self-testing). While any complex system requires testing to ensure satisfactory performance, satellite systems require extensive testing for two additional reasons: they operate in an environment considerably different from that in which they were built, and after launch they are inaccessible to routine maintenance and repair. Because of these unique requirements, a specific solution is required such as a self-contained, autonomous, self-testing circuit. The focus of this thesis is on the design and development of a series of Built-In Self-Tests (BISTs) for use with the Configurable Fault Tolerant Processor (CFTP). The results of this thesis are two detailed designs for a Random Access Memory (RAM) BIST and a Read-Only Memory (ROM) BIST, as well as a conceptual design for a Field Programmable Gate Array (FPGA) BIST. These designs are stored on board the CFTP and are made to operate remotely and autonomously. Together, these BISTs provide a means to monitor, exercise, and test the CFTP components and thus facilitate a reliable design.