LOW-POWER ADDRESS POINTER DESIGN FOR FIFO MEMORY CIRCUITS

• Main Author: Ramamoorthy, Saravanan
• Format: Others
• Published: OpenSIUC 2009
• Online Access: https://opensiuc.lib.siu.edu/theses/446; https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=1453&context=theses

In this work, we developed low-power circuit technique for Complementary Metal Oxide Semiconductor (CMOS) address pointers used in First-In First-Out (FIFO) memories. Traditionally, pointer circuits for FIFO memories can be implemented by using shift register. However such traditional way of implementation increases the number of flip-flops with the increase of the size of the memory. Since the pointer operation is triggered by clock signals, traditional implementation imposes heavy capacitive load on the clock path of the pointer circuit which results in large power consumption of the circuit. We developed a novel pointer circuit which results in significant capacitive load reduction. The new design consists of two types of basic cells referred to as N-cell and P-cell. With this new design each pointer stage only contributes a single gate capacitance to the pointer clock signal path. Also double-edge-triggered clock scheme is used in the design to reduce the switching activities and hence the power consumption on the clock path. Finally, clock gating techniques are presented to further minimize the capacitive load on the clock signal path. Pointer circuits of the proposed design have been implemented using a 65nm CMOS technology. Circuit simulations demonstrate the developed pointer circuit consumes significant less power than the previously proposed low-power pointer circuits implemented with the same technology. The simulation also shows that the proposed circuit is suitable for low voltage applications.