A Radiation Tolerant Phase Locked Loop Design for Digital Electronics

With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential lo...

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Main Author: Kumar, Rajesh
Other Authors: Khatri, Sunil P.
Format: Others
Language:en_US
Published: 2011
Subjects:
Online Access:http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8547
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spelling ndltd-tamu.edu-oai-repository.tamu.edu-1969.1-ETD-TAMU-2010-08-85472013-01-08T10:42:35ZA Radiation Tolerant Phase Locked Loop Design for Digital ElectronicsKumar, RajeshRadiation tolerant circuitsHeavy ionssplit output gatesHardened VCOhardened charge pumphardened PLLWith decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.Khatri, Sunil P.2011-10-21T22:03:33Z2011-10-22T07:13:35Z2011-10-21T22:03:33Z2011-10-22T07:13:35Z2010-082011-10-21August 2010thesistextapplication/pdfhttp://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8547en_US
collection NDLTD
language en_US
format Others
sources NDLTD
topic Radiation tolerant circuits
Heavy ions
split output gates
Hardened VCO
hardened charge pump
hardened PLL
spellingShingle Radiation tolerant circuits
Heavy ions
split output gates
Hardened VCO
hardened charge pump
hardened PLL
Kumar, Rajesh
A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
description With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.
author2 Khatri, Sunil P.
author_facet Khatri, Sunil P.
Kumar, Rajesh
author Kumar, Rajesh
author_sort Kumar, Rajesh
title A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
title_short A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
title_full A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
title_fullStr A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
title_full_unstemmed A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
title_sort radiation tolerant phase locked loop design for digital electronics
publishDate 2011
url http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8547
work_keys_str_mv AT kumarrajesh aradiationtolerantphaselockedloopdesignfordigitalelectronics
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