Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling
This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a memory-efficient low-power high-throughput multi-rate array LDPC decoder as well as...
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| Format: | Others |
| Language: | en_US |
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2010
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2504 http://hdl.handle.net/1969.1/ETD-TAMU-2504 |