Durability of Electrolytes Applied to Printed Field-Effect Transistors
Field effect transistors (FETs) are indispensable for our modern digital society, needed as basic building blocks for logical gates in all digital circuits. FETs are found in sample and hold circuits with high storage capacities and high write and read speeds and in driver circuits for active matrix...
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| Format: | Others |
| Language: | en |
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2017
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| Online Access: | https://tuprints.ulb.tu-darmstadt.de/6668/1/Dissertation_FalkvonSeggern.pdf von Seggern, Falk <http://tuprints.ulb.tu-darmstadt.de/view/person/von_Seggern=3AFalk=3A=3A.html> (2017): Durability of Electrolytes Applied to Printed Field-Effect Transistors.Darmstadt, Technische Universität, [Ph.D. Thesis] |
| Summary: | Field effect transistors (FETs) are indispensable for our modern digital society, needed as basic building blocks for logical gates in all digital circuits. FETs are found in sample and hold circuits with high storage capacities and high write and read speeds and in driver circuits for active matrix displays such as large area TVs. An entire new application perspective is currently emerging in the area of printed electronics, where flexible plastic foils, papers and textiles become inexpensive substrates for novel devices. To realize circuits on such substrates, dielectrics, semiconductors and conductors with suitable morphologies as well as innovative device architectures have to be developed. Prominent among others, printed liquid electrolytes with high gate capacities in combination with printed oxide semiconductors have yielded good device performance and remarkable drain currents at low gate voltages. To be usable in everyday applications basic requirements have to be fulfilled, such as functional stability during environmental temperature changes, sufficient current output to drive more advanced electronic circuits, high switching speed and miniaturized size to allow for large packing densities. Miniaturized high current transistors with good temperature stability can open the path to many new applications for printed electronics, e.g., wearable electronics or lighting solutions, where higher currents are necessary.
In this thesis in-plane indium oxide based FETs have been fabricated utilizing composite solid polymer electrolytes (CSPEs) for gating. Different CSPEs have been investigated to determine the most suitable candidate for high performance FETs concerning chemical, physical and electrical behavior. The CSPE, containing LiClO4, PVA, PC and DMSO, has been selected and printed onto an in-plane electrolyte-gated FET (EG-FET). Special attention has been drawn to the key parameters of the EG-FET like mobility, on-current, on/off-current ratio and threshold voltage tested over a wide temperature range. Especially the temperature independence of the on-current and the threshold voltage as well as the absence of hysteresis turn out to be beneficial with respect to future applicability of printed EG-FETs in electrical circuits.
In order to downsize the in-plane EG-FETs and to obtain large drain currents at the same time, a vertical arrangement of the FET (v-FET) has been realized. In order to achieve this goal, SnO2 has been stacked in between two platinum electrodes to achieve the vertical source/semiconductor/drain structure, in plane with the platinum gate. The gating is realized by ink-jet printing a CSPE film covering the semiconductor channel and the gate. The CSPE, infiltrated into the porous semiconductor network, addresses the entire inner surface of the semiconductor. A channel of 45 nm is achieved by utilizing the thickness of the printed semiconductor film. A device using such geometry yields nearly ideal transistor characteristics with a clear current saturation with increasing drain voltage and a quadratic increase of the output curves with increasing gate voltage. The large drain current densities exceeding 0.1 MA/cm2 can be explained by the large channel area or channel width, which can be modeled by a large number of independent pillars forming conducting pathways between source to drain electrode.
Finally, the problem of limited switching speeds of an in-plane EG-FET has been addressed. The limiting factor for such devices is clearly the large gate-to-channel distance, which limits the time to form the FET conducting channel. The characteristic time constant is determined by the ionic conductivity of the CSPE and double layer capacitance of the CSPE/semiconductor interface. In order to reduce the gate-to-channel distance, i. e., the total resistance, a back-gated EG-FET has been designed using a porous AlOx spacer with a thickness of about 300 nm and a SnO2 layer as the channel material. Due to the reduction of the gate-to-channel distance by more than two orders of magnitude a potential reduction of the the switching frequency can be shown. |
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