Memory Hierarchy Design for Next Generation Scalable Many-core Platforms

Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) re...

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Bibliographic Details
Main Author: Azarkhish, Erfan <1985>
Other Authors: Benini, Luca
Format: Doctoral Thesis
Language:en
Published: Alma Mater Studiorum - Università di Bologna 2016
Subjects:
Online Access:http://amsdottorato.unibo.it/7255/
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spelling ndltd-unibo.it-oai-amsdottorato.cib.unibo.it-72552016-09-13T04:55:50Z Memory Hierarchy Design for Next Generation Scalable Many-core Platforms Azarkhish, Erfan <1985> ING-INF/01 Elettronica Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) requiring fast transfer of large volumes of data, are two main trends which intensify this problem by putting even higher pressure on the memory hierarchy. This increasing gap between computation speed and data transfer speed is commonly referred as the “memory wall” problem. With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years. On one hand, it is now possible to improve memory access bandwidth and/or latency by either stacking memories directly on top of processors or through abstracted memory interfaces such as Micron’s Hybrid Memory Cube (HMC). On the other hand, near memory computation has become worthy of revisiting due to the cost-effective integration of logic and memory in 3D stacks. These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market. In this research, we study the effectiveness of the 3D integration technology and the optimization opportunities which it can provide in the different layers of the memory hierarchy in cluster-based many-core platforms ranging from intra-cluster L1 to inter-cluster L2 scratchpad memories (SPMs), as well as the main memory. In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities. Alma Mater Studiorum - Università di Bologna Benini, Luca 2016-06-09 Doctoral Thesis PeerReviewed application/pdf en http://amsdottorato.unibo.it/7255/ info:eu-repo/semantics/openAccess
collection NDLTD
language en
format Doctoral Thesis
sources NDLTD
topic ING-INF/01 Elettronica
spellingShingle ING-INF/01 Elettronica
Azarkhish, Erfan <1985>
Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
description Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) requiring fast transfer of large volumes of data, are two main trends which intensify this problem by putting even higher pressure on the memory hierarchy. This increasing gap between computation speed and data transfer speed is commonly referred as the “memory wall” problem. With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years. On one hand, it is now possible to improve memory access bandwidth and/or latency by either stacking memories directly on top of processors or through abstracted memory interfaces such as Micron’s Hybrid Memory Cube (HMC). On the other hand, near memory computation has become worthy of revisiting due to the cost-effective integration of logic and memory in 3D stacks. These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market. In this research, we study the effectiveness of the 3D integration technology and the optimization opportunities which it can provide in the different layers of the memory hierarchy in cluster-based many-core platforms ranging from intra-cluster L1 to inter-cluster L2 scratchpad memories (SPMs), as well as the main memory. In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities.
author2 Benini, Luca
author_facet Benini, Luca
Azarkhish, Erfan <1985>
author Azarkhish, Erfan <1985>
author_sort Azarkhish, Erfan <1985>
title Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
title_short Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
title_full Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
title_fullStr Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
title_full_unstemmed Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
title_sort memory hierarchy design for next generation scalable many-core platforms
publisher Alma Mater Studiorum - Università di Bologna
publishDate 2016
url http://amsdottorato.unibo.it/7255/
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