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    A 10-bit 30-MS/s Pipeline ADC for DVB-H Receiver Systems and Mixed-Voltage Tolerant I/O Cell Design
    by Tie-Yan Chang, 張鐵諺
    Published 2007
    “... can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS...”
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