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  1. 1
    Interconnect-driven floorplanning.
    Published 2002
    “... --- Simulated Annealing --- p.23 === Chapter 2.3.6 --- Genetic Algorithm --- p.23 === Chapter 2.4 --- Summary...”
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  2. 2
    Interconnect planning in physical design of VLSI.
    Published 2006
    “... to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process...”
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