“.... Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping...”
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“... (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic...”
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“... to Synopsys, our synthesis results have better area and speed performance. ...”
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“... compared with those obtained using Synopsys logic synthesis tools. ...”
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“... procedures both in the front-end synthesis by Synopsys Design Compiler and the back-end post-layout...”
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“... in the traditional cell-based design flow, including behavior model, Synopsys library, LEF file, Spice netlists...”
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“... with our proposed CSE methods achieve significant area improvement compared with Synopsys optimization...”
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“... synthesized from combination logic using Synopsys RTL (Register Transfer Level) Design Compiler. Based...”
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