Showing 1 - 9 results of 9 for search 'MECHANICAL AND DIGITAL DESIGN', query time: 0.84s Refine Results
  1. 1
    Profiling and reducing micro-architecture bottlenecks at the hardware level
    by Moreira, Francis Birck
    Published 2014
    Subjects: “...Hardware design...”
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  2. 2
    Profiling and reducing micro-architecture bottlenecks at the hardware level
    by Moreira, Francis Birck
    Published 2014
    Subjects: “...Hardware design...”
    Get full text
    Others
  3. 3
    Profiling and reducing micro-architecture bottlenecks at the hardware level
    by Moreira, Francis Birck
    Published 2014
    Subjects: “...Hardware design...”
    Get full text
    Others
  4. 4
    Dynamic detection of the communication pattern in shared memory environments for thread mapping
    “... and drastically increasing the overhead. In this master thesis, we introduce two novel light-weight mechanisms...”
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    Others
  5. 5
    Dynamic detection of the communication pattern in shared memory environments for thread mapping
    “... and drastically increasing the overhead. In this master thesis, we introduce two novel light-weight mechanisms...”
    Get full text
    Others
  6. 6
    Dynamic detection of the communication pattern in shared memory environments for thread mapping
    “... and drastically increasing the overhead. In this master thesis, we introduce two novel light-weight mechanisms...”
    Get full text
    Others
  7. 7
    Increasing energy efficiency of processor caches via line usage predictors
    by Alves, Marco Antonio Zanata
    Published 2014
    “...’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality...”
    Get full text
    Others
  8. 8
    Increasing energy efficiency of processor caches via line usage predictors
    by Alves, Marco Antonio Zanata
    Published 2014
    “...’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality...”
    Get full text
    Others
  9. 9
    Increasing energy efficiency of processor caches via line usage predictors
    by Alves, Marco Antonio Zanata
    Published 2014
    “...’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality...”
    Get full text
    Others
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