Search Results - ELECTRONICS DESIGN

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Design of the distributed Cache for reconfigurable array processor

by Jiang Lin, Liu Yang, Shan Rui, Liu Peng, Geng Yurong
Published 2018-12-01
“...” in reconfigurable array processors is increasing. Traditionally, the use of multi-level shared Cache hardware design...”

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2

Design of texture cache for embedded mobile graphics processing unit

by Han Mengqiao, Jiang Lin, Yang Bowen, Shan Rui, Geng Yurong
Published 2019-05-01
“... parallel reading are designed. FIFO buffer is designed for prefetching memory data and reducing memory...”

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