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  1. 1
    An Optimized Structure on FPGA of Key Point Detection in SIFT Algorithm
    by Xu Chenyu, Zhu En, Su Tiange, Li Xiaoran
    Published 2016-01-01
    Subjects: “...pipeline architecture...”
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    Article
  2. 2
    Projeto de um codificador/decodificador Viterbi integrado
    by Pacheco, Roberto Vargas
    Published 2009
    Subjects: “...Pipeline architecture...”
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  3. 3
    Projeto de um codificador/decodificador Viterbi integrado
    by Pacheco, Roberto Vargas
    Published 2009
    Subjects: “...Pipeline architecture...”
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    Others
  4. 4
    Projeto de um codificador/decodificador Viterbi integrado
    by Pacheco, Roberto Vargas
    Published 2009
    Subjects: “...Pipeline architecture...”
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    Others
  5. 5
    Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES
    Subjects: “...pipeline architecture...”
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    Article
  6. 6
    End-To-End Computer Vision Framework: An Open-Source Platform for Research and Education
    Subjects: “...pipeline architecture...”
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    Article
  7. 7
    Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA
    Subjects: “...pipeline architecture...”
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    Article
  8. 8
    A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks Compared With Titan X GPU
    Subjects: “...pipeline architecture...”
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    Article
  9. 9
    Arquitetura pipeline para processamento morfológico de imagens binárias em tempo real utilizando dispositivos de lógica programável complexa
    by Emerson Carlos Pedrino
    Published 2003
    Subjects: “... Pipeline architecture ...”
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  10. 10
    Arquitetura pipeline para processamento morfológico de imagens binárias em tempo real utilizando dispositivos de lógica programável complexa
    by Pedrino, Emerson Carlos
    Published 2003
    Subjects: “...Pipeline architecture...”
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  11. 11
    Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP
    by Haowen Tian, Shixu Guo, Peng Zhao, Minyu Gong, Chao Shen
    Published 2021-02-01
    Subjects: “...multicore pipeline architecture...”
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    Article
  12. 12
    An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture
    Subjects: “...pipelined architecture...”
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    Article
  13. 13
    FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition
    Subjects: “...pipelined architecture...”
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    Article
  14. 14
    Fpga-Based Dvcpro Hd Decoder Implementation Using Impulse C
    by Slawomir Cichon, Marek Gorgon
    Published 2013-01-01
    Subjects: “...high definition; video decoding; high level languages; pipelined architecture; intra-frame...”
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    Article
  15. 15
    Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs
    by Emerson Carlos Pedrino
    Published 2008
    Subjects: “... Pipelined architecture ...”
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  16. 16
    Arquitetura pipeline reconfigurável através de instruções geradas por programação genética para processamento morfológico de imagens digitais utilizando FPGAs
    by Pedrino, Emerson Carlos
    Published 2008
    Subjects: “...Pipelined architecture...”
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    Others
  17. 17
    An Efficient Barrel Distortion Correction Processor for Bayer Pattern Images
    by Tae-Hwan Kim
    Published 2018-01-01
    Subjects: “...pipelined architecture...”
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    Article
  18. 18
    FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms
    Subjects: “...pipelined architecture...”
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    Article
  19. 19
    Surface Realization Using a Featurized Syntactic Statistical Language Model
    by Packer, Thomas L.
    Published 2006
    Subjects: “...standard pipeline architecture...”
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  20. 20
    An Investigation of Methods to Improve Area and Performance of Hardware Implementations of a Lattice Based Cryptosystem
    by Beckwith, Luke Parkhurst
    Published 2020
    Subjects: “...Pipelined Architecture...”
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